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general description the max15046 synchronous step-down controller oper - ates from a 4.5v to 40v input voltage range and gener - ates an adjustable output voltage from 85% of the input voltage down to 0.6v, supporting loads up to 25a. the device allows monotonic startup into a prebiased bus without discharging the output and features adaptive internal digital soft-start. the max15046 offers the ability to adjust the switching frequency from 100khz to 1mhz with an external resis - tor. the max15046s adaptive synchronous rectifica - tion eliminates the need for an external freewheeling schottky diode. the device also utilizes the external low-side mosfets on-resistance as a current-sense element, eliminating the need for a current-sense resis - tor. this protects the dc-dc components from damage during output overloaded conditions or output short- circuit faults without requiring a current-sense resistor. hiccup-mode current limit reduces power dissipation during short-circuit conditions. the max15046 includes a power-good output and an enable input with precise turn-on/turn-off threshold, which can be used for input supply monitoring and for power sequencing. additional protection features include sink-mode current limit, and thermal shutdown. sink-mode current limit pre - vents reverse inductor current from reaching dangerous levels when the device is sinking current from the output. the max15046a/MAX15046B feature soft-stop opera - tion. soft-stop operation is disabled in the max15046c. the max15046 is available in a 16-pin qsop or 16-pin qsop-ep package and operates over the -40 c to +125c temperature range. features s input voltage ranges from 4.5v to 40v or 5v q10% s adjustable outputs from 0.85 x v in down to 0.6v s adjustable switching frequency (100khz to 1mhz) with q10% (1mhz) accuracy s adaptive internal digital soft-start s up to 25a output capability s cycle-by-cycle valley-mode current limit with adjustable, temperature-compensated threshold (30mv to 300mv) s monotonic startup into prebiased output s q1% accurate voltage reference s 90% maximum duty cycle (max15046c) s 3a peak gate drivers s hiccup-mode short-circuit protection s overtemperature shutdown s power-good (pgood) output and enable input (en) with q5% accurate threshold s thermally enhanced 16-pin qsop package applications industrial power supplies (plc, industrial computers, fieldbus components, fieldbus couplers) telecom power supplies base stations 19-4719; rev 2; 1/13 ordering information and pin configurations appear at end of data sheet. max15046 in v cc dh csp lx bst dl drv pgnd gnd c1 q1 q2 pgood en lim comp fb rt l1 0.6v to 0.85v x v in v out d1 r5 c4 c3 c2 r2 r3 r3 c6 c5 r4 4.5v to 40v v in on off c7 r1 40v, high-performance, synchronous buck controller max15046 evaluation kit available typical operating circuit for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in to gnd .............................................................. -0.3v to +45v v cc to gnd ..................... -0.3v to lower of (v in + 0.6v) and 6v en, drv to gnd ..................................................... -0.3v to +6v pgood to gnd .................................................... -0.3v to +45v pgnd to gnd ...................................................... -0.3v to +0.3v dl to pgnd ............................................. -0.3v to (v drv + 0.3v) bst to pgnd ....................................................... -0.3v to +50v lx and csp to pgnd ............................................... -1v to +45v lx and csp to pgnd ............................ -2v (50ns max) to +45v bst to lx ................................................................. -0.3v to +6v csp to lx ............................................................. -0.3v to +0.3v dh to lx .................................................. -0.3v to (v bst + 0.3v) all other pins to gnd .............................. -0.3v to (v cc + 0.3v) v cc short circuit to gnd .......................................... continuous pgood maximum sink current ......................................... 20ma continuous power dissipation (t a = +70nc): 16-pin qsop (derate 9.6mw/ nc above +70nc) ....... 771.5mw 16-pin qsop-ep (derate 22.7mw/ n c above +70n c) 1818.2mw operating temperature range ........................ -40nc to +125nc junction temperature ..................................................... +150nc storage temperature range ............................ -65nc to +150nc lead temperature (soldering, 10s) ................................ +300nc soldering temperature (reflow) ...................................... +260nc electrical characteristics (v in = 24v, v en = 5v, v gnd = v pgnd = 0v, c in = 1ff, c vcc = 4.7ff, r rt = 49.9ki, t a = t j = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 2) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to http://www.maximintegrated.com/thermal-tutorial. qsop junction-to-ambient thermal resistance ( q ja ) .... +103.7c/w junction-to-case thermal resistance ( q jc ) .............. +37c/w qsop-ep junction-to-ambient thermal resistance ( q ja ) ......... +44c/w junction-to-case thermal resistance ( q jc ) ................ +6c/w package thermal characteristics (note 1) parameter symbol conditions min typ max units system specifications input-voltage range v in 4.5 40 v v in = v cc = v drv 4.5 5.5 quiescent supply current i in_q v in = 24v, v fb = 0.9v, no switching 2 3 ma shutdown supply current i in_sby v in = 24v, v en = 0v, i vcc = 0, pgood = unconnected 0.35 0.55 ma v cc regulator output voltage v cc 6v v in 40v, i load = 6ma 5 5.25 5.5 v v cc regulator dropout v in = 4.5v, i load = 25ma 0.18 0.45 v v cc short-circuit output current v in = 5v 30 55 90 ma v cc undervoltage lockout v ccuvlo v cc rising 3.8 4 4.2 v v cc undervoltage lockout hysteresis 400 mv error amplifier (fb, comp) fb input-voltage set point v fb 584 590 596 mv fb input bias current i fb v fb = 0.6v -250 +250 na fb to comp transconductance g m i comp = q20fa 600 1200 1800 fs open-loop gain 80 db unity-gain bandwidth capacitor from comp to gnd = 47pf 5 mhz maxim integrated 40v, high-performance, synchronous buck controller max15046
3 electrical characteristics (continued) (v in = 24v, v en = 5v, v gnd = v pgnd = 0v, c in = 1ff, c vcc = 4.7ff, r rt = 49.9ki, t a = t j = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 2) parameter symbol conditions min typ max units v comp-ramp minimum voltage 200 mv comp source/sink current i comp v comp = 1.4v 50 80 110 fa enable (en) en input high v en_h v en rising 1.14 1.20 1.26 v en input low v en_l v en falling 1.05 v en input leakage current i en v en = 5.5v -1 +1 fa oscillator switching frequency (100khz) f sw r rt = 150ki 80 100 120 khz switching frequency (300khz) f sw r rt = 49.9ki 270 300 330 khz switching frequency (1mhz) f sw r rt = 14.3ki 0.9 1 1.1 mhz switching frequency adjustment range (note 3) 100 1000 khz rt voltage v rt r rt = 49.9ki 1.15 1.2 1.25 v pwm modulator pwm ramp peak-to-peak amplitude v ramp 1.5 v pwm ramp valley v valley max15046a/b 1.5 v max15046c 0.75 minimum controllable on-time 70 125 ns maximum duty cycle d max f sw = 300khz (r rt = 49.9ki) max15046a/b 85 87.5 % max15046c 90 93 minimum low-side on-time f sw = 1mhz (r rt = 14.3ki) max15046a/b 110 ns max15046c 90 output drivers/drivers supply (v drv ) undervoltage lockout v drv_uvlo v drv rising 4.0 4.2 4.4 v drv undervoltage lockout hysteresis 400 mv dh on-resistance low, sinking 100ma, v bst - v lx = 5v 1 3 i high, sourcing 100ma, v bst - v lx = 5v 1.5 4 dl on-resistance low, sinking 100ma, v drv = v cc = 5.25v 1 3 high, sourcing 100ma, v drv = v cc = 5.25v 1.5 4 dh peak current c load = 10nf sinking, v bst - v lx = 5v 3 a sourcing, v bst - v lx = 5v 2 maxim integrated 40v, high-performance, synchronous buck controller max15046
4 electrical characteristics (continued) (v in = 24v, v en = 5v, v gnd = v pgnd = 0v, c in = 1ff, c vcc = 4.7ff, r rt = 49.9ki, t a = t j = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 2) note 2: all devices are 100% tested at room temperature and guaranteed by design over the specified temperature range. note 3: select r rt as: 9 rt -7 2 sw sw 17.3 10 r f (1 x 10 )( f ) = + , where f sw is in hertz. parameter symbol conditions min typ max units dl peak current c load = 10nf sinking, v drv = v cc = 5.25v 3 a sourcing, v drv = v cc = 5.25v 2 dh, dl break-before-make time (dead time) max15046a/b 10 ns max15046c 20 soft-start soft-start duration 2048 switching cycles reference voltage steps 64 steps current limit/hiccup cycle-by-cycle valley current- limit threshold adjustment range v csp - v pgnd , valley limit = v lim /10 v lim = 0.3v 30 mv v lim = 3v 300 lim reference current i lim v lim = 0.3v to 3v, t a = +25nc 45 50 55 fa lim reference current temperature coefficient 2300 ppm/nc csp input bias current v csp = 40v -1 +1 fa number of consecutive current- limit events to hiccup 7 events hiccup timeout 4096 switching cycles peak low-side sink current-limit threshold v csp - v pgnd , sink limit = v lim /20, r ilim = 30ki, v lim = 1.5v, t a = +25nc 75 mv power-good (pgood) pgood threshold v fb rising 90 94 97.5 %v fb pgood threshold hysteresis v fb falling 2.65 %v fb pgood output low voltage v pgood_l i pgood = 2ma, v en = 0v 0.4 v pgood output leakage current i leak_pgood v pgood = 40v, v en = 5v, v fb = 1v -1 +1 fa thermal shutdown thermal shutdown threshold temperature rising +150 nc thermal shutdown hysteresis 20 nc maxim integrated 40v, high-performance, synchronous buck controller max15046
5 typical operating characteristics (v in = 24v, t a = +25nc, unless otherwise noted.) efficiency vs. load current (v in = 24v) max15046 toc01 load current (a) efficiency (%) 12 9 6 3 10 20 30 40 50 60 70 80 90 100 0 01 5 v out = 5v v out = 3.3v v out = 1.8v v out = 1.2v efficiency vs. load current (v in = 12v) max15046 toc02 load current (a) efficiency (%) 12 9 6 3 10 20 30 40 50 60 70 80 90 100 0 01 5 v out = 5v v out = 3.3v v out = 1.8v v out = 1.2v v out vs. load current load current (a) % output from normal 10 8 6 4 2 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 01 2 max15046 toc03 v cc vs. load current load current (ma) v cc (v) 5.244 5.246 5.248 5.250 5.252 5.254 5.256 5.242 max15046 toc04 40 35 30 25 20 15 10 5 04 5 v cc line regulation v in (v) v cc (v) 3530252015105 4.0 4.2 4.4 4.6 4.8 5.0 5.2 04 0 max15046 toc05 i vcc = 5ma, 10ma, 20ma, 30ma i vcc = 40ma v cc vs. temperature temperature (nc) v cc (v) 110 95 80 65 50 35 20 5 -10 -25 5.261 5.262 5.263 5.264 5.265 5.266 5.260 -40 125 max15046 toc06 i load = 5ma switching frequency vs. r rt r rt (ki) frequency (khz) 120 80 40 100 200 300 400 500 600 700 800 900 1000 0 0 160 max15046 toc07 switching frequency vs. temperature temperature (nc) frequency (khz) 110 95 80 65 50 35 20 5 -10 -25 200 400 600 800 1000 1200 0 -40 125 max15046 toc08 r t = 14.3ki r t = 25.5ki r t = 49.9ki r t = 150ki i in vs. switching frequency max15046 toc09 frequency (khz) i in (ma) 2.3 2.4 2.5 2.6 2.7 2.8 2.2 100 1000 c dh = c dl = 0 maxim integrated 40v, high-performance, synchronous buck controller max15046
6 typical operating characteristics (continued) (v in = 24v, t a = +25nc, unless otherwise noted.) lim reference current vs. temperature temperature (nc) current (fa) 110 95 -25 -10 5 35 50 65 20 80 45 50 55 60 65 70 75 80 40 -40 125 max15046 toc10 sink and source current limit thresholds vs. resistance (r ilim ) resistance (ki) current-limit threshold (v) 60 50 30 40 20 10 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.35 07 0 max15046 toc11 sink current limit source current limit load transient on out (1a to 10a) max15046 toc12a i out 5a/div v out 200mv/div 200fs/div load transient on out (1a to 15a) max15046 toc12b i out 5a/div v out 200mv/div 200fs/div load transient on out (1a to 6a) max15046 toc12c i out 5a/div v out 100mv/div 200fs/div startup disable from en (r load = 3.3i) (max15046a/b) max15046 toc13 v out 2v/div pgood 5v/div in 20v/div en 5v/div 4ms/div startup and disable from in (r load = 3.3ki) max15046 toc14 v out 2v/div pgood 5v/div in 10v/div 20ms/div startup with prebiased output (4.0v) max15046 toc15a v out 2v/div pgood 5v/div in 10v/div 24v 4v 4ms/div startup with prebiased output (1.0v) max15046 toc15b v out 2v/div pgood 5v/div in 10v/div 24v 1v 4ms/div maxim integrated 40v, high-performance, synchronous buck controller max15046
7 typical operating characteristics (continued) (v in = 24v, t a = +25nc, unless otherwise noted.) startup with prebiased output (0.5v) max15046 toc15d v out 2v/div pgood 5v/div v in 10v/div 24v 0.5v 4ms/div v out = 3.3v startup with prebiased output (2v) max15046 toc15c v out 2v/div pgood 5v/div in 10v/div 24v 2v 4ms/div v out = 3.3v sink current-limit waveforms (5v prebiased) max15046 toc16 v lx 50v/div i lx 5a/div v out 500mv/div 200fs/div line-transient response max15046 toc19 v in 10v/div 5v 24v v out (ac-coupled) 200mv/div 10ms/div output short-circuit behavior max15046 toc18 v out 200mv/div i out 10a/div 10ms/div break-before-make time (dl_ falling to dh_ rising) max15046 toc17b v dl 5v/div v lx 20v/div v dh 20v/div 40ns/div break-before-make time (dh_ falling to dl_ rising) max15046 toc17a v dl 5v/div v lx 20v/div v dh 20v/div 40ns/div maxim integrated 40v, high-performance, synchronous buck controller max15046
8 pin description pin name function 1 in regulator input. connect to the input rail of the buck converter. bypass in to pgnd with a 100nf minimum ceramic capacitor. when operating in the 5v q10% range, connect in to v cc . 2 v cc 5.25v linear regulator output. bypass v cc to pgnd with a ceramic capacitor of at least 4.7 ff when v cc supplies mosfet gate-driver current at drv or 2.2 ff when v cc is not used to power drv. 3 pgood open-drain power-good output. pull up pgood to an external power supply or output with an external resistor. 4 en active-high enable input. pull en to gnd to disable the buck converter output. connect to v cc for always-on operation. en can be used for power sequencing and as a uvlo adjustment input. 5 lim current-limit input. connect a resistor from lim to gnd to program the current-limit threshold from 30mv (r lim = 6ki) to 300mv (r lim = 60ki). 6 comp error-amplifier output. connect compensation network from comp to fb or from comp to gnd. 7 fb feedback input (inverting input of error amplifier). connect fb to a resistive divider between the buck converter output and gnd to adjust the output voltage from 0.6v up to 0.85 x in. 8 rt oscillator-timing resistor input. connect a resistor from rt to gnd to set the oscillator frequency from 100khz to 1mhz. 9 gnd analog ground. connect pgnd and agnd together at a single point. 10 pgnd power ground. use pgnd as a return path for the low-side mosfet gate driver. 11 drv gate-driver supply voltage. drv is internally connected to the low-side driver supply. bypass drv to pgnd with a 2.2 f f minimum ceramic capacitor (see the typical application circuits ). 12 dl low-side external mosfet gate-driver output. dl swings from drv to pgnd. 13 bst boost flying capacitor connection. internally connected to the high-side driver supply. connect a ceramic capacitor of at least 100nf between bst and lx and a diode between bst and drv for the high-side mosfet gate-driver supply. 14 lx inductor connection. also serves as a return terminal for the high-side mosfet driver current. connect lx to the switching side of the inductor. 15 dh high-side external mosfet gate-driver output. dh swings from bst to lx. 16 csp current-sense positive input. connect to the drain of low-side mosfet with kelvin connection. ep exposed pad. connect ep to a large copper ground plane to maximize thermal performance. maxim integrated 40v, high-performance, synchronous buck controller max15046
9 functional diagram dc-dc oscillator and enable logic en_int vref vref v_bgap bgap_ok enable comparator bgap_ok shutdown vl_ok pwm comparator pwm dh bst lx csp ramp hiccup vref ck ck enable oscillator osc enable ramp generator bandgap ok generator v cc rt en lim v cc uvlo vin_ok i bias vin_ok v ref = 0.6v v bgap = 1.24v in in uvlo vin_ok v_bgap vdrv_ok drv uvlo bgap_ok bgap_ok v_drv internal voltage regulator vin_ok thermal shutdown and ilim current generator main bias current generator bandgap reference fb dac_vref hiccup timeout dh_dl_enable vref ck soft-start/stop and hiccup logic g m comp ck dh_dl_enable hiccup timeout pwm control logic lim/10 lim/20 sink current-limit comparator pgood comparator valley current-limit comparator high- side driver hiccup max15046 dl drv pgnd fb pgood gnd low- side driver vref enable maxim integrated 40v, high-performance, synchronous buck controller max15046
10 detailed description the max15046 synchronous step-down controller oper - ates from a 4.5v to 40v input-voltage range and gener - ates an adjustable output voltage from 85% of the input- voltage down to 0.6v while supporting loads up to 25a. as long as the device supply voltage is within 5.0v to 5.5v, the input power bus (v in ) can be as low as 3.3v. the max15046 offers adjustable switching frequency from 100khz to 1mhz with an external resistor. the adjustable switching frequency provides design flex - ibility in selecting passive components. the max15046 adopts an adaptive synchronous rectification to elimi - nate external freewheeling schottky diodes and improve efficiency. the device utilizes the on-resistance of the external low-side mosfet as a current-sense element. the current-limit threshold voltage is resistor-adjustable from 30mv to 300mv and is temperature-compensated, so that the effects of the mosfet r ds(on) variation over temperature are reduced. this current-sensing scheme protects the external components from damage during output overloaded conditions or output short- circuit faults without requiring a current-sense resistor. hiccup-mode current limit reduces power dissipation during short-circuit conditions. the max15046 includes a power-good output and an enable input with precise turn-on/-off threshold to be used for monitoring and for power sequencing. the max15046 features internal digital soft-start that allows prebias startup without discharging the output. the digital soft-start function employs sink current limiting to prevent the regulator from sinking excessive current when the prebias voltage exceeds the programmed steady- state regulation level. the digital soft-start feature prevents the synchronous rectifier mosfet and the body diode of the high-side mosfet from experiencing dangerous lev - els of current while the regulator is sinking current from the output. the max15046 shuts down at a +150n c junction temperature to prevent damage to the device. dc-dc pwm controller the max15046 step-down controller uses a pwm volt- age-mode control scheme (see the functional diagram). control-loop compensation is external for providing max - imum flexibility in choosing the operating frequency and output lc filter components. an internal transconduc - tance error amplifier produces an integrated error volt - age at comp that helps to provide higher dc accuracy. the voltage at comp sets the duty cycle using a pwm comparator and a ramp generator. on the rising edge of an internal clock, the high-side n-channel mosfet turns on and remains on until either the appropriate duty cycle or the maximum duty cycle is reached. during the on-time of the high-side mosfet, the inductor cur- rent ramps up. during the second-half of the switching cycle, the high-side mosfet turns off and the low-side n-channel mosfet turns on. the inductor releases the stored energy as the inductor current ramps down, pro - viding current to the output. under overload conditions, when the inductor current exceeds the selected valley current-limit threshold (see the current-limit circuit (lim) section), the high-side mosfet does not turn on at the subsequent clock rising edge and the low-side mosfet remains on to let the inductor current ramp down. internal 5.25v linear regulator an internal linear regulator ( v cc ) provides a 5.25v nomi - nal supply to power the internal functions and to drive the low-side mosfet. connect in and v cc together when using an external 5v q10% power supply. the maximum regulator input voltage (v in ) is 40v. bypass in to gnd with a 1ff ceramic capacitor. bypass the output of the linear regulator (v cc ) with a 4.7 ff ceramic capacitor to gnd. the v cc dropout voltage is typically 180mv. when v in is higher than 5.5v, v cc is typically 5.25v. the max15046 also employs an undervoltage lockout circuit that disables the internal linear regulator when v cc falls below 3.6v (typical). the 400mv uvlo hysteresis pre - vents chattering on power-up/power-down. mosfet gate drivers (dh, dl) dh and dl are optimized for driving large-size n-channel power mosfets. under normal operating conditions and after startup, the dl low-side drive waveform is always the complement of the dh high-side drive waveform, with controlled dead time to prevent cross - conduction or shoot-through. an adaptive dead-time circuit monitors the dh and dl outputs and prevents the opposite-side mosfet from turning on until the mosfet is fully off. thus, the circuit allows the high-side driver to turn on only when the dl gate driver has turned off and prevents the low side (dl) from turning on until the dh gate driver has turned off. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimiz - ing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from dl and dh to the mosfet gates for the adaptive dead-time circuits maxim integrated 40v, high-performance, synchronous buck controller max15046
11 to function properly. the stray impedance in the gate discharge path can cause the sense circuitry to interpret the mosfet gate as off while the v gs of the mosfet is still high. to minimize stray impedance, use very short, wide traces. synchronous rectification reduces conduction losses in the rectifier by replacing the normal low-side schottky catch diode with a low-resistance mosfet switch. the max15046 features a robust internal pulldown transistor with a typical 1i r ds(on) to drive dl low. this low on- resistance prevents dl from being pulled up during the fast rise time of the lx node, due to capacitive coupling from the drain to the gate of the low-side synchronous rectifier mosfet. high-side gate-drive supply (bst) an external schottky diode between bst and dh is required to boost the gate voltage above lx providing the necessary gate-to-source voltage to turn on the high- side mosfet. the boost capacitor connected between bst and lx holds up the voltage across the gate driver during the high-side mosfet on-time. the charge lost in the boost capacitor for delivering the gate charge is replenished when the high-side mosfet turns off and the lx node goes to ground. when lx is low, the external diode between v drv and bst recharg - es the boost capacitor. see the boost capacitor and diode selection section in the applications information to choose the right boost capacitor and diode. enable input (en), soft-start, and soft-stop drive en high to turn on the max15046. a soft-start sequence starts to increase (step-wise) the reference voltage of the error amplifier. the duration of the soft- start ramp is 2048 switching cycles and the resolution is 1/64th of the steady-state regulation voltage allowing a smooth increase of the output voltage. a logic-low on en initiates a soft-stop sequence by stepping down the ref - erence voltage of the error amplifier. after the soft-stop sequence is completed, the mosfet drivers are both turned off. see figure 1. soft-stop operation is disabled for the max15046c. connect en to v cc for always-on operation. owing to the accurate turn-on/-off thresholds, en can be used as a uvlo adjustment input, and for power sequencing together with the pgood outputs. figure 1. power on-off sequencing v cc b cd e 2048 clock cycles 2048 clock cycles f g hi a uvlo en v out dac_vref dh dl uvlo undervoltage threshold value is provided in the electrical characteristics table. internal 5.25v linear regulator output. active-high enable input. regulator output voltage. regulator internal soft-start and soft-stop signal. regulator high-side gate-driver output. regulator low-side gate-driver output. v cc rising while below the uvlo threshold. en is low. v cc en v out dac_vref dh dl a symbol definition b v cc is higher than the uvlo threshold. en is low. en is pulled high. dh and dl start switching. normal operation. v cc drops below uvlo. v cc goes above the uvlo threshold. dh and dl start switching. normal operation. en is pulled low. v out enters soft-stop. en is pulled high. dh and dl start switching. normal operation. v cc drops below uvlo. c d e f g h i symbol definition maxim integrated 40v, high-performance, synchronous buck controller max15046
12 when the valley current limit is reached during soft-start, the max15046 regulates to the output impedance times the limited inductor current and turns off after 4096 clock cycles. when starting up into a large capacitive load (for example), the inrush current will not exceed the current- limit value. if the soft-start is not completed before 4096 clock cycles, the device turns off. the device remains off for 8192 clock cycles before trying to soft-start again. this implementation allows the soft-start time to be automatically adapted to the time necessary to keep the inductor current below the limit while charging the output capacitor. power-good output (pgood) the max15046 includes a power-good comparator to monitor the output voltage and detect the power-good threshold, fixed at 93% of the nominal fb voltage. the open-drain pgood output requires an external pullup resistor. pgood sinks up to 2ma of current while low. pgood goes high (high-z) when the regulator output increases above 93% of the designed nominal regulated voltage. pgood goes low when the regulator output volt - age drops to below 90% of the nominal regulated voltage. pgood asserts low during the hiccup timeout period. startup into a prebiased output when the max15046 starts into a prebiased output, dh and dl are off so that the converter does not sink current from the output. dh and dl do not start switching until the pwm comparator commands the first pwm pulse. the first pwm pulse occurs when the ramping reference voltage increases above the fb voltage. when the output voltage is biased above the output set point, the controller tries to pull the output down to the set point once the internal soft-start is complete. this pulldown is controlled by the sink current limit, which is slowly increased to its normal value to minimize output undershoot. current-limit circuit (lim) the current-limit circuit employs a valley and sink current-sensing algorithm that uses the on-resistance of the low-side mosfet as a current-sensing element, to eliminate costly sense resistors. the current-limit circuit is also temperature compensated to track the on-resistance variation of the mosfet overtemperature. the current limit is adjustable with an external resistor at lim and accommodates mosfets with a wide range of on-resistance characteristics (see the setting the valley current limit section). the adjustment range is from 0.3v to 3v for the valley current limit, corresponding to resistor values of 6ki to 60ki. the valley current-limit threshold across the low-side mosfet is precisely 1/10th of the voltage at lim, while the sink current-limit threshold is 1/20th of the voltage at lim. valley current limit acts when the inductor current flows towards the load, and csp is more negative than pgnd during the low-side mosfet on-time. if the magnitude of the current-sense signal exceeds the valley current-limit threshold at the end of the low-side mosfet on-time, the max15046 does not initiate a new pwm cycle and lets the inductor current decay in the next cycle. the control - ler also rolls back the internal reference voltage so that the controller finds a regulation point determined by the current-limit value and the resistance of the short. in this manner, the controller acts as a constant current source. this method greatly reduces inductor ripple current during the short event, which reduces inductor sizing restrictions and reduces the possibility for audible noise. after 4096 clock cycles, the device goes into hiccup mode. once the short is removed, the internal reference voltage soft-starts back up to the normal reference volt - age and regulation continues. sink current limit is implemented by monitoring the volt - age drop across the low-side mosfet when csp is more positive than pgnd. when the voltage drop across the low-side mosfet exceeds 1/20 th of the voltage at lim at any time during the low-side mosfet on-time, the low-side mosfet turns off and the inductor current flows from the output through the body diode of the high-side mosfet. when the sink current limit activates, the dh/ dl switching sequence is no longer complementary and both mosfets are turned off. carefully observe the pcb layout guidelines to ensure that noise and dc errors do not corrupt the current- sense signals at csp and pgnd. mount the max15046 close to the low-side mosfet with short, direct traces making a kelvin-sense connection so that trace resis - tance does not add to r ds(on) of the low-side mosfet. hiccup mode overcurrent protection hiccup mode overcurrent protection reduces power dissipation during prolonged short-circuit or severe overload conditions. an internal 3-bit counter counts up on each switching cycle when the valley current-limit threshold is reached. the counter counts down on each switching cycle when the threshold is not reached, and stops at zero (000). when the current-limit condition persists and the counter reaches 111 (= 7 events), the maxim integrated 40v, high-performance, synchronous buck controller max15046
13 max15046 stops both dl and dh drivers and waits for 4096 switching cycles (hiccup timeout delay) before attempting a new soft-start sequence. the hiccup-mode protection remains active during the soft-start time. undervoltage lockout the max15046 provides an internal undervoltage lock - out (uvlo) circuit to monitor the voltage on v cc . the uvlo circuit prevents the max15046 from operating when v cc is lower than v uvlo . the uvlo threshold is 4v, with 400mv hysteresis to prevent chattering on the rising/falling edge of the supply voltage. dl and dh stay low to inhibit switching when the device is in undervolt - age lockout. thermal-overload protection thermal-overload protection limits total power dissipa - tion in the max15046. when the junction temperature of the device exceeds +150 n c, an on-chip thermal sensor shuts down the device, forcing dl and dh low, which allows the device to cool. the thermal sensor turns the device on again after the junction temperature cools by 20nc. the regulator shuts down and soft-start resets during thermal shutdown. power dissipation in the ldo regulator and excessive driving losses at dh/dl trigger thermal-overload protection. carefully evaluate the total power dissipation (see the power dissipation section) to avoid unwanted triggering of the thermal-overload pro - tection in normal operation. applications information effective input-voltage range the max15046 operates from 4.5v to 40v input supplies and regulates output down to 0.6v. the minimum voltage conversion ratio (v out /v in ) is limited by the minimum controllable on-time. for proper fixed-frequency pwm operation, the voltage conversion ratio must obey the following condition: out on(min) sw in v tf v > where t on(min) is 125ns and f sw is the switching fre - quency in hertz. pulse skipping occurs to decrease the effective duty cycle when the desired voltage conversion does not meet the above condition. decrease the switch - ing frequency or lower the input voltage v in to avoid pulse skipping. the maximum voltage conversion ratio is limited by the maximum duty cycle (d max ): + < out max drop2 max drop1 max in in v d v (1-d ) v d- vv where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pcb resistance. v drop2 is the sum of the voltage drops by the resistance in the charg - ing path, including high-side switch, inductor, and pcb resistance. in practice, provide adequate margin to the above conditions for good load-transient response. setting the output voltage set the max15046 output voltage by connecting a resis - tive divider from the output to fb to gnd (figure 2). select r 2 from between 4ki and 16ki. calculate r 1 with the following equation: ?? ?? = ?? ?? ?? ?? ?? out 12 fb v r r -1 v where v fb = 0.59v (see the electrical characteristics table) and v out can range from 0.6v to (0.85 o v in ). resistor r 1 also plays a role in the design of the type iii compensation network. review the values of r 1 and r 2 when using a type iii compensation network (see the type iii compensation network (figure 4) section). figure 2. adjustable output voltage fb r 1 out r 2 max15046 maxim integrated 40v, high-performance, synchronous buck controller max15046
14 setting the switching frequency an external resistor connecting rt to gnd sets the switching frequency (f sw ). the relationship between f sw and r rt is: 9 rt -7 2 sw sw 17.3 10 r f (1x10 ) x (f ) = + where f sw is in hz and r rt is in i. for example, a 300khz switching frequency is set with r rt = 49.9ki. higher frequencies allow designs with lower inductor values and less output capacitance. peak currents and i 2 r losses are lower at higher switching frequencies, but core losses, gate-charge currents, and switching losses increase. inductor selection three key inductor parameters must be specified for operation with the max15046: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dc ). to determine the inductance, select the ratio of inductor peak-to-peak ac current to dc average cur - rent (lir) first. for lir values that are too high, the rms currents are high, and therefore i 2 r losses are high. use high-valued inductors to achieve low lir values. typically, inductor resistance is proportional to induc - tance for a given package type, which again makes i 2 r losses high for very low lir values. a good compromise between size and loss is a 30% peak-to-peak ripple cur - rent to average-current ratio (lir = 0.3). the switching frequency, input voltage, output voltage, and selected lir determine the inductor value as follows: out in out in sw out v(v-v) l v f i lir = where v in , v out , and i out are typical values. the switching frequency is set by r t (see setting the switching frequency section). the exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, and efficiency. lower inductor val- ues minimize size and cost, but also improve transient response and reduce efficiency due to higher peak cur - rents. on the other hand, higher inductance increases efficiency by reducing the rms current. find a low-loss inductor with the lowest possible dc resistance that fits in the allotted dimensions. the saturation current rating (i sat ) must be high enough to ensure that saturation cannot occur below the maximum current-limit value (i cl(max) ), given the tolerance of the on-resistance of the low-side mosfet and of the lim reference current (i lim ). combining these conditions, select an inductor with a saturation current (i sat ) of: ? sat cl(typ) i 1.35 i where i cl(typ) is the typical current-limit set point. the factor 1.35 includes r ds(on) variation of 25% and 10% for the lim reference current error. a variety of inductors from different manufacturers are available to meet this requirement (for example, vishay ihlp-4040dz-1-5 and other inductors from the same series). setting the valley current limit the minimum current-limit threshold must be high enough to support the maximum expected load current with the worst-case low-side mosfet on-resistance value as the r ds(on) of the low-side mosfet is used as the current- sense element. the inductors valley current occurs at i load(max) minus one half of the ripple current. the minimum value of the current-limit threshold voltage (v ith ) must be higher than the voltage on the low-side mosfet during the ripple-current valley, ith ds(on,max) load(max) lir vr i 1 2 ? ?? > ?? ?? where r ds(on,max) in i is the maximum on-resistance of the low-side mosfet at maximum load current i load(max) and is calculated from the following equation: ds(on,max) ds(on) mosfet max amb r r [1 tc ( t - t ) ] = + where r ds(on) (in i is the on-resistance of the low- side mosfet at ambient temperature t amb (in degrees celsius), tc mosfet is the temperature coefficient of the low-side mosfet in ppm/ n c, and t max (in degrees celsius) is the temperature at maximum load current i load(max) . obtain the r ds(on) and tc mosfet from the mosfet data sheet. maxim integrated 40v, high-performance, synchronous buck controller max15046
15 connect an external resistor (r lim ) from lim to gnd to adjust the current-limit threshold, which is temper - ature-compensated with a temperature coefficient of 2300ppm/nc. the relationship between the current-limit threshold (v ith ) and r lim is: ith lim -6 max amb) 10 v r ppm 50 10 1 2300 (t - t c = ?? + ?? ?? where r lim is in i, v ith is in v, t max and t amb are in nc. an r lim resistance range of 6k i to 60k i corresponds to a current-limit threshold of 30mv to 300mv. use 1% tolerance resistors when adjusting the current limit to minimize error in the current-limit threshold. input capacitor the input filter capacitor reduces peak current drawn from the power source and reduces noise and voltage ripple on the input caused by the switching circuitry. the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents as defined by the following equation: out in out rms load(max) in v(v-v) ii v = i rms attains a maximum value when the input volt - age equals twice the output voltage (v in = 2v out ), so i rms(max) = i load(max)/2 . for most applications, nontantalum capacitors (ceramic, aluminum, polymer, or os-con) are preferred at the inputs due to the robust - ness of nontantalum capacitors to accommodate high inrush currents of systems being powered from very low impedance sources. additionally, two (or more) smaller- value low-esr capacitors should be connected in paral - lel to reduce high-frequency noise. output capacitor the key selection parameters for the output capacitor are capacitance value, esr, and voltage rating. these parameters affect the overall stability, output ripple volt - age, and transient response. the output ripple has two components: variations in the charge stored in the output capacitor, and the voltage drop across the capacitors esr caused by the current flowing into and out of the capacitor: dv ripple = dv esr + dv q the output-voltage ripple as a consequence of the esr and the output capacitance is: esr p-p p-p q out sw in out out p-p sw in v i esr i v 8c f v -v v i fl v ?= ?= ?? ?? = ?? ?? ?? ?? where i p-p is the peak-to-peak inductor current ripple (see the inductor selection section). use these equa- tions for initial capacitor selection. decide on the final values by testing a prototype or an evaluation circuit. check the output capacitor against load-transient response requirements. the allowable deviation of the output voltage during fast load transients determines the capacitor output capacitance, esr, and equivalent series inductance (esl). the output capacitor supplies the load current during a load step until the controller responds with a higher duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the converter (see the compensation design section). the resistive drop across the esr of the output capaci - tor, the voltage drop across the esl ( dv esl ) of the capacitor, and the capacitor discharge, cause a voltage droop during the load step. use a combination of low-esr tantalum/aluminum elec - trolytic and ceramic capacitors for improved transient load and voltage ripple performance. nonleaded capac- itors and capacitors in parallel help reduce the esl. keep the maximum output-voltage deviation below the tolerable limits of the load. use the following equations to calculate the required esr, esl, and capacitance value during a load step: ? = = ? ? = ? esr step step response out q esl step step response o v esr i it c v vt esl i 1 t 3f where i step is the load step, t step is the rise time of the load step, t response is the response time of the control - ler, and f o is the closed-loop crossover frequency. maxim integrated 40v, high-performance, synchronous buck controller max15046
16 compensation design the max15046 provides an internal transconductance amplifier with the inverting input and the output available for external frequency compensation. the flexibility of external compensation offers wide selection of output filtering components, especially the output capacitor. use high-esr aluminum electrolytic capacitors for cost- sensitive applications. use low-esr tantalum or ceramic capacitors at the output for size-sensitive applications. the high switching frequency of the max15046 allows the use of ceramic capacitors at the output. choose all passive power components to meet the output ripple, component size, and component cost requirements. choose the compensation components for the error amplifier to achieve the desired closed-loop bandwidth and phase margin. to choose the appropriate compensation network type, the power-supply poles and zeros, the zero-crossover frequency, and the type of the output capacitor must be determined first. in a buck converter, the lc filter in the output stage intro - duces a pair of complex poles at the following frequency: = po out out 1 f 2l c the output capacitor introduces a zero at: = zo out 1 f 2 esr c where esr is the equivalent series resistance of the output capacitor. the loop-gain crossover frequency (f o ), where the loop gain equals 1 (0db) should be set below 1/10th of the switching frequency: sw o f f 10 choosing a lower crossover frequency reduces the effects of noise pickup into the feedback loop, such as jittery duty cycle. to maintain a stable system, two stability criteria must be met: 1) the phase shift at the crossover frequency, f o , must be less than 180n. in other words, the phase margin of the loop must be greater than zero. 2) the gain at the frequency where the phase shift is -180n (gain margin) must be less than 1. maintain a phase margin of around 60 n to achieve a robust loop stability and well-behaved transient response. when using an electrolytic or large-esr tantalum output capacitor, the capacitor esr zero f zo typically occurs between the lc poles and the crossover frequency f o (f po < f zo < f o ). choose the type ii (pi-proportional, integral) compensation network. when using a ceramic or low-esr tantalum output capacitor, the capacitor esr zero typically occurs above the desired crossover frequency f o , that is f po < f o < f zo . choose the type iii (pid- proportional, integral, and derivative) compensation network. type ii compensation network (figure 3) if f zo is lower than f o and close to f po , the phase lead of the capacitor esr zero almost cancels the phase loss of one of the complex poles of the lc filter around the cross - over frequency. use a type ii compensation network with a midband zero and a high-frequency pole to stabilize the loop. in figure 3, r f and c f introduce a midband zero (f z1 ). r f and c cf in the type ii compensation net - work provide a high-frequency pole (f p1 ), which mitigates the effects of the output high-frequency ripple. use the following steps to calculate the component values for type ii compensation network as shown in figure 3: 1) calculate the gain of the modulator (gain mod ), comprised of the regulators pulse-width modulator, lc filter, feedback divider, and associated circuitry at crossover frequency: ( ) = in fb mod ramp o out out vv esr gain v 2f l v where v in is the input voltage of the regulator, v ramp is the amplitude of the ramp in the pulse-width modula - tor, v fb is the fb input voltage set point (0.6v typically, see the electrical characteristics table), and v out is the desired output voltage. the gain of the error amplifier (gain ea ) in midband frequencies is: gain ea = g m x r f where g m is the transconductance of the error amplifier. maxim integrated 40v, high-performance, synchronous buck controller max15046
17 the total loop gain, which is the product of the modulator gain and the error-amplifier gain at f o , is: ( ) mod ea in fb mf osc o out out f osc o out out f fb in m 1) gain gain 1 so : vv esr gr1 v (2 f l ) v solving for r : v 2f l v r v v g esr = = = 2) set a midband zero (f z1 ) at 0.75 x f po (to cancel one of the lc poles): = = z1 po ff 1 f 0.75 f 2r c solving for c f : = f f po 1 c 2 r f 0.75 3) place a high-frequency pole at f p1 = 0.5 x f sw (to attenuate the ripple at the switching frequency f sw ) and calculate c cf using the following equation: = cf f sw f 1 c 1 rf- c type iii compensation network (figure 4) when using a low-esr tantalum or ceramic type, the esr-induced zero frequency is usually above the tar - geted zero crossover frequency (f o ). use type iii com - pensation. type iii compensation provides two zeros and three poles at the following frequencies: = = + z1 ff z2 i 1i 1 f 2r c 1 f 2 c (r r ) two midband zeros (f z1 and f z2 ) cancel the pair of com- plex poles introduced by the lc filter: f p1 = 0 f p1 introduces a pole at zero frequency (integrator) for nulling dc output-voltage errors: = p2 ii 1 f 2 rc depending on the location of the esr zero (f zo ), use f p2 to cancel f zo , or to provide additional attenuation of the high-frequency output ripple: = + p3 f cf f f cf 1 f cc 2r cc f p3 attenuates the high-frequency output ripple. place the zeros and poles such that the phase margin peaks around f o . ensure that r f >> 2/g m and the parallel resistance of r 1 , r 2 , and r i is greater than 1/g m . otherwise, a 180 n phase shift is introduced to the response making the loop unstable. use the following compensation procedures: 1) with r f >> 10k i , place the first zero (f z1 ) at 0.8 x f po : = = z1 po ff 1 f 0.8 f 2r c figure 3. type ii compensation network v ref r 1 v out r 2 g m r f comp c f c cf maxim integrated 40v, high-performance, synchronous buck controller max15046
18 so: = f f po 1 c 2 r 0.8 f 2) the gain of the modulator (gain mod ), comprised of the pulse-width modulator, lc filter, feedback divider, and associated circuitry at crossover frequency is: = in mod 2 ramp o out out v 1 gain v (2 f ) l c the gain of the error amplifier (gain ea ) in midband frequencies is: = ea o i f gain 2 f c r the total loop gain as the product of the modulator gain and the error amplifier gain at f o is 1. ( ) mod ea in o if 2 ramp o out out i ramp o out out i in f gain gain 1 so : v 1 2 f cr 1 v (2 f ) c l solving for c : v 2f l c c vr = = = 3) use the second pole (f p2 ) to cancel f zo when f po < f o < f zo < f sw/2 . the frequency response of the loop gain does not flatten out soon after the 0db crossover, and maintains -20db/decade slope up to 1/2 of the switching frequency. this is likely to occur if the output capacitor is low-esr tantalum. set f p2 = f zo . when using a ceramic capacitor, the capacitor esr zero (f zo ) is likely to be located even above one half of the switching frequency, f po < f o < f sw/2 < f zo . in this case, place the frequency of the second pole (f p2 ) high enough in order not to significantly erode the phase margin at the crossover frequency. for example, set f p2 at 5 x f o so that the contribution to phase loss at the crossover frequency f o is only about 11 n: f p2 = 5 x f o once f p2 is known, calculate r i : = i p2 i 1 r 2f c 4) place the second zero (f z2 ) at 0.2 x f o or at f po , whichever is lower and calculate r 1 using the following equation: 1i z2 i 1 r -r 2f c = 5) place the third pole (f p3 ) at one half the switching frequency and calculate c cf : ( ) f cf sw f f c c 2 0.5 f r c - 1 = 6) calculate r 2 as: = ? fb 21 out fb v rr vv mosfet selection the max15046 step-down controller drives two exter - nal logic-level n-channel mosfets. the key selection parameters to choose these mosfets include: u on-resistance (r ds(on) ) u maximum drain-to-source voltage (v ds(max) ) u minimum threshold voltage (v th(min) ) u total gate charge (q g ) u reverse transfer capacitance (c rss ) u power dissipation the two n-channel mosfets must be a logic-level type with guaranteed on-resistance specifications at v gs = 4.5v. for maximum efficiency, choose a high- side mosfet that has conduction losses equal to the switching losses at the typical input voltage. ensure that the conduction losses at minimum input voltage do not exceed the mosfet package thermal limits, or violate the overall thermal budget. also ensure that the conduc - tion losses plus switching losses at the maximum input voltage do not exceed package ratings or violate the maxim integrated 40v, high-performance, synchronous buck controller max15046
19 overall thermal budget. ensure that the dl gate driver can drive the low-side mosfet. in particular, check that the dv/dt caused by the high-side mosfet turning on does not pull up the low-side mosfet gate through the drain-to-gate capacitance of the low-side mosfet, which is the most frequent cause of crossconduction problems. check power dissipation when using the internal linear regulator to power the gate drivers. select mosfets with low gate charge so that v cc can power both drivers without overheating the device: p drive = v cc x q g_total x f sw where q g_total is the sum of the gate charges of the two external mosfets. boost capacitor and diode selection the max15046 uses a bootstrap circuit to generate the necessary gate-to-source voltage to turn on the high-side mosfet. the selected n-channel high-side mosfet determines the appropriate boost capacitance value (c bst in the typical application circuits) accord- ing to the following equation: = ? g bst bst q c v where q g is the total gate charge of the high-side mosfet and dv bst is the voltage variation allowed on the high-side mosfet driver after turn-on. choose dv bst such that the available gate-drive voltage is not significantly degraded (e.g. dv bst = 100mv to 300mv) when determining c bst . use a low-esr ceramic capacitor as the boost capacitor with a minimum value of 100nf. a small-signal diode can be used for the bootstrap cir - cuit and must have a minimum voltage rating of v in + 3v to withstand the maximum bst voltage. the average forward current of the diode should meet the following requirement: i f > q gate x f sw where q gate is the gate charges of the high-side mosfet. power dissipation the maximum power dissipation of the device depends on the thermal resistance from the die to the ambient environment and the ambient temperature. the thermal resistance depends on the device package, pcb copper area, other thermal mass, and airflow. the power dissipated into the package (p t ) depends on the supply configuration (see the typical application circuits). use the following equation to calculate power dissipation: p t = v in x [q g_total x f sw + i q ] where i q is the quiescent supply current at the switching frequency. see the i in vs. switching frequency graph in the typical operating characteristics for the i q . use the following equation to estimate the temperature rise of the die: t j = t a + (p t x b ja ) where b ja is the junction-to-ambient thermal impedance of the package, p t is power dissipated in the device, and t a is the ambient temperature. the b ja is 103.7n c/w for the 16-pin qsop and 44n c/w for the 16-pin qsop- ep package on multilayer boards, with the conditions specified by the respective jedec standards (jesd51-5, jesd51-7). an accurate estimation of the junction tem - perature requires a direct measurement of the case temperature (t c ) when actual operating conditions significantly deviate from those described in the jedec standards. the junction temperature is then: t j = t c + (p t x b jc ) use 37nc/w as b jc thermal impedance for the 16-pin qsop package and 6nc/w for the 16-pin qsop-ep package. the case-to-ambient thermal impedance (b ca ) is dependent on how well the heat is transferred from the pcb to the ambient. use large copper areas to keep the pcb temperature low. figure 4. type iii compensation network v ref g m r 1 r 2 v out r i comp c i c cf r f c f maxim integrated 40v, high-performance, synchronous buck controller max15046
20 pcb layout guidelines careful pcb layout is critical to achieve clean and stable operation. the switching power stage requires particular attention. follow these guidelines for good pcb layout: 1) place decoupling capacitors as close as possible to the ic. connect the power ground plane (connected to pgnd) and signal ground plane (connected to gnd) at one point near the device. 2) connect input and output capacitors to the power ground plane; connect all other capacitors to the sig - nal ground plane. 3) keep the high-current paths as short and wide as possible. keep the path of switching current (c2 to in and c2 to pgnd) short. avoid vias in the switching paths. 4) connect csp to the drain of the low-side fet using a kelvin connection for accurate current-limit sensing. 5) ensure all feedback connections are short and direct. place the feedback resistors as close as possible to the ic. 6) route high-speed switching nodes (bst, lx, dh, and dl) away from sensitive analog areas (rt, fb, comp, and lim). 24v supply, 3.3v output operation typical application circuit 1 in the typical application circuits section shows an application circuit that oper - ates out of 24v and outputs up to 10a at 3.3v. r5 sets the switching frequency to 350khz. single 4.5v to 5.5v supply operation typical application circuit 2 in the typical application circuits section shows an application circuit for a single +4.5v to +5.5v power-supply operation. auxiliary 5v supply operation typical application circuit 3 in the typical application circuits section shows an application circuit for a +24v supply to drive the external mosfets and an auxiliary +5v supply to power the device maxim integrated 40v, high-performance, synchronous buck controller max15046
21 typical application circuits max15046 in typical application circuit 1 v cc dh csp lx bst dl drv pgnd gnd q1 q1: vishay siliconix si7850dp q2: vishay siliconix si7460dp d1: diodes inc. zhcs506 l1: vishay ihlp-4040pz er1r5m c1: panasonic eevfk1h101p c8, c9: murata grm31cr60j476k q2 pgood en lim comp fb rt l1 1.5fh v out +3.3v d1 c6 2.2ff c8 100ff c10 47ff c4 0.1ff c3 10ff c2 10ff c5 0.47ff r4 105ki r5 43.2ki c16 1ff r9 32.4ki v in +24v c13 68pf c15 15pf c12 220pf c14 1500pf r6 23.2ki c1 100ff r2 2.2i r7 51ki on off r8 22.6ki r3 3.65ki c11 4.7ff c9 100ff r1 10i c7 1000pf maxim integrated 40v, high-performance, synchronous buck controller max15046
22 typical application circuits (continued) max15046 in v cc dh csp lx bst dl drv pgnd gnd c2 q1 q2 pgood en lim comp fb rt l1 v out d1 c6 c4 c5 c3 r2 r3 r3 c8 c7 r4 v in +4.5v to +5.5v pgood enable c9 r1 c1 typical application circuit 2 max15046 in v cc dh csp lx bst dl drv pgnd gnd c2 q1 q2 pgood en lim comp fb rt l1 v out d1 c6 c4 c5 c3 r2 r3 r3 c8 c7 r4 v aux +4.5v to +5.5v v in +24v pgood enable c9 r1 c1 typical application circuit 3 maxim integrated 40v, high-performance, synchronous buck controller max15046
23 chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code document no. 16 qsop e16+4 21-0055 16 qsop-ep e16e+9 21-0112 pin configurations ordering information + denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. the max15046c is recommended for new designs. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in csp dh lx bst dl drv pgnd gnd top view max15046a qsop v cc pgood comp en lim fb rt + 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in csp dh lx bst dl drv pgnd gnd qsop-ep v cc pgood comp en lim fb rt exposed pad + MAX15046B max15046c part temp range pin-package max15046aaee+ -40 c to +125 c 16 qsop MAX15046Baee+ -40 c to +125 c 16 qsop-ep* max15046caee+ -40 c to +125 c 16 qsop-ep* maxim integrated 40v, high-performance, synchronous buck controller max15046
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 24 maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/09 initial release 1 2/10 corrected minimum low-side on-time conditions in electrical characteristics; corrected tocs 2, 18, and 19; corrected mosfet gate drivers (dh, dl) , setting the switching frequency, setting the valley current limit, mosfet selection, and power dissipation sections; corrected typical application circuit 1 3, 5, 7, 10, 14, 15, 18, 19, 21 2 1/13 added max15046c 1, 3, 4, 6C8, 11 40v, high-performance, synchronous buck controller max15046

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